Connection bit order between hierarchy - Connection bit order between hierarchy Hi, I got unintended bit order of bus connection between SystemVerilog top with Block Design in lower hierarchy. I intend to connect inst3 to out[3] but Quartus connected in reversed order. Please see Technology map viewer screen shot and open archived project. Is there any Quartus option to fix this problem? This happens with (System)Verilog top only. I already experiment bdf, tdf, vhd top instead of sv, they work as expected. I am using Quartus Pro 23.2. Thanks, Masaru Replies: Re: Connection bit order between hierarchy Hi Masaru, Thank you for the update and for taking the time to work with us. I will proceed with closing this ticket. However, we will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions. Thank you for engaging with us! Best regards, ZiYingE_Altera Replies: Re: Connection bit order between hierarchy Hi Zi Ying, Ok, I am happy with your workarounds. I agree with closing this ticket. Thank you for your help. Masaru Replies: Re: Connection bit order between hierarchy Hi Masaru, Thank you for the clarification. After confirming once again with the Altera design team using the original design along with the information from the additional forum link that have been provided, this issue has been identified as a known software bug. As BDF has been deprecated and is no longer supported in newer Quartus releases, no fix is planned for this issue. Here are some of the suggested workaround you may work with: 1. Avoid using .bdf files by converting them to Verilog or VHDL in Quartus Prime Standard Edition using File → Create/Update → Create HDL Design File from Current File, and then use the generated HDL files in Quartus Prime Pro. 2. Replace the SystemVerilog top-level module with a VHDL, AHDL, or BDF top-level design to avoid the bus-ordering issue. 3. Continue using your existing workaround with the streaming operator (<<) to resolve the bus ordering. We understand this may not be the outcome you were hoping for, and we apologize for the inconvenience. Please feel free to reach out if you have any further questions or concerns. If there are no further questions or updates, we may proceed with closing the support ticket accordingly. Best regards, ZiYingE_Altera Replies: Re: Connection bit order between hierarchy 1. Does the original design that reports the following error contain a BDF module in its hierarchy? Yes, please see my experiment #8. and #10. for detail. 2. When testing the DDR3 example design targeting the Cyclone 10 GX Development Kit that fails without error, was the same BDF module or hierarchy used? No, the example design from altera is not .sv to .bdf hierarchy structure. Replies: Re: Connection bit order between hierarchy Hi Masaru, Thank you for the additional details. After discussing with the Altera design team again, there is currently no better workaround than using ".Out({<<{Out}})" for two dimensional signals, as BDF is no longer supported starting from Quartus Prime Pro Edition 23.3. Based on your previous post, may I check a few additional details? 1. Does the original design that reports the following error contain a BDF module in its hierarchy? Error(13135): Address/command pin (ddr3_a[0]) is constrained to an illegal location (PIN_AG19). The legal location for this pin is PIN_Y17 2. When testing the DDR3 example design targeting the Cyclone 10 GX Development Kit that fails without error, was the same BDF module or hierarchy used? Thank you! Best regards, ZiYingE_Altera Replies: Re: Connection bit order between hierarchy Hi Zi Ying, Thank you for detailed workaround methods. You discovered that Quartus Standard version doesn't have this issue. I didn't know that. For "Create HDL Design File from Current File" workaround, it works for two-dimensional signals. It is good for me. For "Use Quartus Prime Standard Edition" workaround, my target device of actual project is Cyclone 10 GX, so this workaround is not available. Please see my another post for my real project: https://community.altera.com/discussions/quartus-prime/error13135-addresscommand-pin-is-constrained-to-an-illegal-location/353620/ This strange error in the post has the same root as our discussion. Masaru Replies: Re: Connection bit order between hierarchy Hi Masaru, Thank you for your patience. The issue you are seeing is related to a bug in Quartus Prime Pro during the elaboration of a System Verilog module that instantiates a BDF module. However, since BDF support has been deprecated in Quartus Prime Pro Edition starting from version 23.3, this issue is not planned to be fixed. As a workaround, you may: Convert all BDF files to Verilog or VHDL You can use Quartus Prime Standard Edition to perform the conversion: Create and open a Quartus project. Open the target BDF file. Select File → Create/Update → Create HDL Design File from Current File . Choose either Verilog or VHDL as the output format. After the conversion, please use the generated HDL files in place of the original BDF modules. I've attached the connection after replacing the .bdf file with the generated .v file for your reference. The attachment is named replacing_bdf_with_verilog_connection.png. Use Quartus Prime Standard Edition You can also use for the Quartus Prime Standard Edition. I have tested the design with it and the SystemVerilog design able to instantiate BDF successfully. The Quartus Version that I am using was Quartus Prime Standard Edition 24.1. I have attached the connection diagram for your reference. The attachment is named quartus_standard_connection.png We sincerely apologize for the inconvenience. Please feel free to let us know if you have any other questions. Best regards, ZiYingE_Altera Replies: Re: Connection bit order between hierarchy Zi Ying, Thank you for the information. .Out({<<{Out}}) also works. I have checked this workaround for two-dimensional packed array. If the Block Design entry goes on, I am happy that altera would fix this issue. Masaru Replies: Re: Connection bit order between hierarchy Hi Masaru, Thank you for sharing the detailed description and QAR. There is no Quartus option to prevent this reversal. After review, this behavior is caused by a mismatch between SystemVerilog packed array ordering and Block Design indexing. SystemVerilog buses follow a fixed MSB-to-LSB order Block Design treats signals as an indexed list of bits Because of this difference, Quartus connects signals based on their position (index), which results in a reversed connection. For example: Block Design: inst0 → index 0 inst1 → index 1 inst2 → index 2 inst3 → index 3 SystemVerilog: Out = [3] [2] [1] [0] MSB to LSB Quartus maps by position: index 0 → Out[3] index 1 → Out[2] index 2 → Out[1] index 3 → Out[0] Resulting in: inst0 → Out[3] inst1 → Out[2] inst2 → Out[1] inst3 → Out[0] The recommended workaround is to explicitly reorder the bits in the top-level module: assign Out = {bdf_out[0], bdf_out[1], bdf_out[2], bdf_out[3]}; This manually restores the intended mapping. I have also attached back the QAR for your reference. Best regards, Zi Ying