Stratix V Hard IP for PCI Express IP Core May Fail Link Training - Stratix V Hard IP for PCI Express IP Core May Fail Link Training Description The Stratix V Hard IP for PCI Express IP Core may fail link training and remain in the Detect.Quiet state. This failure is caused by an incomplete reset of the TX PMA resulting in a missing internal clock. Resolution This issue is fixed starting with version 12.1 SP1 DP6G of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']