How to design a 1-out-of-3 clock multiplex - How to design a 1-out-of-3 clock multiplex Hi! I'd like to use a clock mux, e.g., altclkctrl, to select one of the 3 clocks generated by a PLL. Unfortunately, I can't use altclkctrl because Stratix III's altclkctrl only provides 2 inputs. And, I can't cascade two altclkctrl because its input can only be clock pin or PLL's ouput clock. I'm wondering if there is any way I can design a 1-out-of-3 clock multiplex? Here is my configuration: Terasic DE3 (Stratix III) + Quartus 13.1 Replies: Re: How to design a 1-out-of-3 clock multiplex Hi JonWay, OK, I understand. Thanks for your prompt reply and help! I wish you a good day! Replies: Re: How to design a 1-out-of-3 clock multiplex You can use the Quartus assignment as Global Signal. Steps are as described in this kdb: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd03182011_985.html Replies: Re: How to design a 1-out-of-3 clock multiplex Hi JonWay, Thanks for your reply and suggestion. That Verilog code's function should be OK. And, how should I ensure that the output clock will use the global clock network, as that clock will drive a lot of circuit in our design? Replies: Re: How to design a 1-out-of-3 clock multiplex Perhaps you can consider implementing it in the core logic. You can refer to: https://courses.cs.washington.edu/courses/cse467/08au/labs/Resources/Recommended%20HDLCoding%20Styles.pdf Page 56. You will need to evaluate if this works for you.