Why is corrupted receiving data seen on the Bursting Avalon-MM Master (BAM) Interface when using Multi Channel DMA FPGA IP for PCI Express*? - Why is corrupted receiving data seen on the Bursting Avalon-MM Master (BAM) Interface when using Multi Channel DMA FPGA IP for PCI Express*? Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1 and earlier, you may see data corruption occur on the Bursting Avalon-MM Master (BAM) Interface of the Multi-Channel DMA FPGA IP for PCI Express, particularly if extensive backpressure is applied to the incoming data stream. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 25.1. Download and install the following patch to fix this problem in the Quartus Prime Pro Edition Software version 25.1. This problem is fixed beginning with the Quartus® Prime Pro Edition software version 25.1.1. Custom Fields values: ['novalue'] Troubleshooting 15018496311, 15018258165 False ['Multi Channel DMA F-Tile for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.1.1 25.1 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']