Why does the "Show PCIe Hard Interface Pins" option in the pin planner for the Cyclone® V GX (5CGXFC5C6U19A7) device variant only show one PCIe Hard IP? - Why does the "Show PCIe Hard Interface Pins" option in the pin planner for the Cyclone® V GX (5CGXFC5C6U19A7) device variant only show one PCIe Hard IP? Description Due to a problem in the Quartus® II software version 13.1 update 4 and later, the "Show PCIe Hard Interface Pins” for the Cyclone® V GX (5CGXFC5C6U19A7) device variant only shows one PCIe® Hard IP. Resolution This device variant supports two Hard PCIe Hard IP's at the following locations 1st PCIe HARD IP Location AA2/AA1(Receiver), Y4/Y3(Transmitter) nPERSTL1 PIN_R17 2nd PCIe HARD IP Location D4/D3(Receiver), C2/C1(Transmitter) nPERSTL0 PIN_R16 Custom Fields values: ['novalue'] Troubleshooting 2205732612 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] No plan to fix 13.1.4 ['Cyclone® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']