Why does the 25G Ethernet Intel® FPGA IP Avalon® Memory-Mapped management interface hang when attempts are made to access out of bounds undefined register address? - Why does the 25G Ethernet Intel® FPGA IP Avalon® Memory-Mapped management interface hang when attempts are made to access out of bounds undefined register address? Description The 25G Ethernet Intel® FPGA IP incorrectly asserts the " waitrequest " signal of Avalon® Memory-Mapped management interface when users attempt to access an undefined out of bounds register address. This can cause the master to hold its current command indefinitely and halt next access from being processed. Resolution The issue has been fixed starting in the Intel® Quartus® Prime Pro software version 20.4 onwards. Custom Fields values: ['novalue'] Troubleshooting 1508553519 False ['25G Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.4 20.3 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']