Internal Error: Sub-system: FYGR, File: /quartus/fitter/fygr/fygr_cdr_op.cpp, Line: 2875 - Internal Error: Sub-system: FYGR, File: /quartus/fitter/fygr/fygr_cdr_op.cpp, Line: 2875 Description Due to a problem in the Quartus® Prime Standard Edition Software version 19.1 or earlier, you may see this internal error when the I/O standard is assigned to LVDS, but this pin is not connected to the LVDS IP. This problem only occurs in MAX® V CPLD devices. Resolution To work around the problem, change the I/O standard from LVDS to another type of I/O standard if the pins are not connected to the LVDS IP. Custom Fields values: ['novalue'] Troubleshooting 1508017938 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] No plan to fix 19.1 ['MAX® V CPLDs'] ['novalue'] ['novalue'] ['novalue']