SDC File Provided With Interlaken MegaCore Function Includes Overly Agressive Timing Path Cuts - SDC File Provided With Interlaken MegaCore Function Includes Overly Agressive Timing Path Cuts Description The Synopsys Design Constraints Files ( .sdc ) provided with the Interlaken MegaCore function cuts all timing relationships between clocks. This constraint is not overly agressive for the design examples, but it does not provide a good example for developing a customer design. If you use this .sdc with your own design, your design might not function correctly in hardware. Resolution In your own design, ensure you do not cut timing paths gratuitously. Do not rely on the .sdc files provided with the IP core for examples of how to make only the necessary timing path cuts. This issue is fixed in version 11.0 of the Interlaken MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['Interlaken'] ['FPGA Dev Tools Quartus II Software'] 11.0 10.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']