Why do I see different HPS IO hashes on SDM-based FPGA designs with HPS First boot mode, where the HPS EMIF IP is not instantiated? - Why do I see different HPS IO hashes on SDM-based FPGA designs with HPS First boot mode, where the HPS EMIF IP is not instantiated? Description Due to a problem in Quartus® Prime Pro Edition Software version 24.1 and earlier, the HPS IO hash generated for Phase 1 and Phase 2 bitstreams may change between builds if the HPS EMIF is not instantiated in an HPS-enabled design. This affects designs where boot mode is set to ' HPS First '. Resolution You may use the QSF assignment to avoid this problem : set_global_assignment -name INI_VARS "asm_constant_hpsio_hash = on" This is scheduled to be fixed in a future release of Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 18038551909 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 24.1 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']