Why do I get a fatal error when running Timing Analysis (Signoff)? - Why do I get a fatal error when running Timing Analysis (Signoff)? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2 and earlier, you may see a fatal error during Timing Analysis (Signoff) or when running the check_timing command in Timing Analyzer. This problem occurs when analyzing clocks for Design Assistant rule checks. Resolution To work around this problem, disable the following Design Assistant Rules CLK-30036 to CLK-30042 TMC-20011 to TMC-20004 This problem is fixed beginning with version 21.3 of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 18017478563 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 21.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']