How to use "set_clock_groups" properly to constrain 2 asynchronous clocks in different clock domains - How to use "set_clock_groups" properly to constrain 2 asynchronous clocks in different clock domains Hello, In my project, I have two different clock domains: 1. The first domain use the " sys_clk " from 10[MHz] external oscillator. 2. The second domain use the " pll_clk " (60[MHz]) that generated by PLL module from source of 100[MHz] external oscillator. It says that the setup time slack of pll_clk is negative, I see the worst-case timing paths, I found that the launch clock is sys_clk ,and the latch clock is pll_clk . Those two clocks are completely unrelated (have different ideal clock sources), when I'm trying to use the "set_clock_groups" definition In my SDC file, as follow: set_clock_groups -asynchronous -group {sys_clk} -group {uart_pll|altpll_component|auto_generated|pll|clk[1]} I get those two warning messages: Warning (332174): Ignored filter at project.sdc(67): " uart_pll|altpll_component|auto_generated|pll|clk[1]" could not be matched with a clock Warning (332049): Ignored set_clock_groups at project.sdc(67): Argument -group with value uart_pll|altpll_component|auto_generated|pll|clk[1] could not match any element of the following types: ( clk ) I don't know how to resolve it, I will be glad to learn from your experience. Replies: Re: How to use "set_clock_groups" properly to constrain 2 asynchronous clocks in different clock domains Hi Aizik Amos, I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Best regards, KhaiY Replies: Re: How to use "set_clock_groups" properly to constrain 2 asynchronous clocks in different clock domains Hi, I tried it and it worked perfectly! Thanks a lot, really appreciate it. Best Regards, Aizik Amos. Replies: Re: How to use "set_clock_groups" properly to constrain 2 asynchronous clocks in different clock domains Hi, Have you tried ak6dn's suggestion? Thanks Best regards, KhaiY Replies: Re: How to use "set_clock_groups" properly to constrain 2 asynchronous clocks in different clock domains (duplicate but I can't delete it) Replies: Re: How to use "set_clock_groups" properly to constrain 2 asynchronous clocks in different clock domains Here's what I did. Works as expected. create_clock -period 20.0 -name CLOCK_50 [get_ports {CLOCK_50}] create_generated_clock -source {pll|altpll_component|pll|inclk[0]} -divide_by 5 -multiply_by 8 -duty_cycle 50 -name CPUCLK {pll|altpll_component|pll|clk[0]} create_generated_clock -source {pll|altpll_component|pll|clk[0]} -divide_by 5000 -duty_cycle 50 -name RTCCLK {dk8ea_clock:rtc|rtcclk} set_clock_groups -asynchronous -group {CLOCK_50} -group {CPUCLK} -group {RTCCLK} -group {altera_reserved_tck} Note you use the NAME of the clock groups in the set_clock_groups command, not the signal or pin names.