Internal Error: Sub-system: FDRGN, File: /quartus/fitter/fdrgn/fdrgn_expert.cpp, Line: 5438 - Internal Error: Sub-system: FDRGN, File: /quartus/fitter/fdrgn/fdrgn_expert.cpp, Line: 5438 Description Due to a problem in the Quartus® Prime Pro Edition Software version 22.4 or earlier, you may see this internal error if your project assigns output pins, other than HPS EMIF pins or GPIO output pins, to the dedicated HPS EMIF I/O bank. This internal error occurs when the Timing Analyzer is invoked after running a full design compilation. Resolution To work around this problem, remove the output pins from the dedicated HPS EMIF I/O Bank and place them in a different location. Place only HPS EMIF pins or GPIO output pins in the dedicated HPS EMIF I/O Bank. Starting with the Quartus® Prime Pro Edition Software version 23.1, this internal error will appear as an error message. Custom Fields values: ['novalue'] Troubleshooting 15017429029 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.4 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']