Why is the parameter ‘pll_slf_rst’ set to false when PLL auto reset is enabled in the PLL FPGA IP in Stratix® V/Arria® V/Cyclone® V devices? - Why is the parameter ‘pll_slf_rst’ set to false when PLL auto reset is enabled in the PLL FPGA IP in Stratix® V/Arria® V/Cyclone® V devices? Description In the Quartus® Prime Standard Edition Software version 23.1 and earlier, you might see the parameter pll_slf_rst is set to false under the Analysis & Synthesis section of the compilation report in designs targeting the Stratix® V/Arria® V/Cyclone® V devices, even though the PLL auto-reset feature is enabled in the PLL FPGA IP. Resolution The PLL FPGA IP auto-reset feature in the Stratix® V/Arria® V/Cyclone® V devices is enabled during the Fitter stage. It does not rely on the RTL parameter pll_slf_rst . You can ignore pll_slf_rst in the Analysis & Synthesis section of the compilation report. To check if PLL auto reset is enabled in the Quartus® Prime Standard Edition Software version 22.1 and earlier, follow these steps: Open the instantiated PLL Intel® FPGA IP in MegaWizard. Switch to Advanced Parameters tab. Check the value of PLL Auto Reset parameter. To check if PLL auto reset is enabled in the Quartus® Prime Standard Edition Software version 23.1, follow these steps: Open the compilation report. Open the PLL Usage Summary report under the Fitter section. Check the value of IOPLL Self RST. Custom Fields values: ['novalue'] Troubleshooting 15012854328 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 23.1 22.1 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']