Incorrect F2SDRAM Data Width Display in Platform Designer for the Arria® 10 HPS IP - Incorrect F2SDRAM Data Width Display in Platform Designer for the Arria® 10 HPS IP Description In the Platform Designer, when configuring the Arria® 10 HPS IP, selecting "Port Configuration 4" under the "FPGA-to-HPS SDRAM Interface" does not update the displayed F2SDRAM data widths accordingly in the GUI. This may confuse, as the expected width values do not reflect the chosen configuration. Resolution This is just a visual bug; this doesn't require a workaround. This is scheduled to be fixed in a later release of Quartus® Prime Software. Custom Fields values: ['novalue'] Troubleshooting 22020913594 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.3 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']