50G Interlaken IP Core Does Not Support 200 MHz _usr_clk Clocks - 50G Interlaken IP Core Does Not Support 200 MHz _usr_clk Clocks Description The 50G Interlaken IP core does not support user clocks ( rx_usr_clk and tx_usr_clk ) with frequency less than 250 MHz. If you provide an input tx_usr_clk clock whose frequency is less than 250 MHz, the IP core will experience internal FIFO underflow, which is flagged with the itx_hungry and itx_underflow flags. If you provide an input rx_usr_clk clock whose frequency is less than 250 MHz, the IP core will experience internal FIFO overflow and data loss from the Interlaken link. Resolution This issue has no workaround. This issue is fixed in version 13.0 SP1 of the 50G Interlaken MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.0.1 13.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']