Why is the o_rx_pfc signal asserted incorrectly when using the F-Tile Ethernet Hard IP in 400GE mode? - Why is the o_rx_pfc signal asserted incorrectly when using the F-Tile Ethernet Hard IP in 400GE mode? Description Due to a problem in the F-Tile Ethernet Hard IP in 400GE mode, situations can exist where the Hard IP receives back-to-back PFC frames, the 2nd PFC frame may incorrectly clear the PFC counters for unrelated queues, causing these queues to stop being back-pressured as intended. The issue only occurs when ALL of the following conditions are met: 1.) The 2nd PFC frame is sent before the quanta of the 1st PFC frame expires 2.) The Priority Enable Vector (PEV) of the 2nd PFC frame has some of the same classes enabled as the 1st PFC frame 3.) The packet arrangement on the RX MAC MII interface is such that the 2nd PFC frame’s PEV and End-of-Packet appear in the same MII clock cycle 4.) No other type of frame is sent between the two PFC frames Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15017410220 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']