Why does the awready signal from the AXI* Switch toggle when using Intel® Stratix® 10 MX HBM2 controller? - Why does the awready signal from the AXI* Switch toggle when using Intel® Stratix® 10 MX HBM2 controller?
Description This is the expected behavior of the AXI* Switch when enabling pseudo BL8. The AXI* Switch needs to wait for the write data transfer of the transaction to complete before receiving the next write request. This will not impact the efficiency of the AXI* interface.
Custom Fields values:
['novalue']
Troubleshooting
1507991354
False
['External Memory Interfaces Stratix® 10 FPGA IP']
['FPGA Dev Tools Quartus® Prime Software Pro']
20.1
20.1
['Stratix® 10 MX FPGA']
['novalue']
['novalue']
['novalue'] - 2021-08-25
external_document