How do you use the DQS phase-shift circuit when the memory interface frequency is below the DLL minimum reference clock frequency? - How do you use the DQS phase-shift circuit when the memory interface frequency is below the DLL minimum reference clock frequency? Description The DQS phase-shift circuit uses a DLL to dynamically control the clock delay required by the DQS/CQ/CQn/QK# pins. In turn, the DLL uses a frequency reference to dynamically generate control signals for the delay chains in each DQS/CQ/CQn/QK# pin, allowing it to compensate for process, voltage, and temperature (PVT) variations. The DQS phase-shift circuit can still be used to ensure effective phase-shift for memory interfaces running below the minimum 200MHz DLL input frequency. Resolution Follow these guidelines: 1) For an interface frequency between 100MHz - 199MHz, the frequency of the clock feeding the DLL should be doubled to achieve an effective phase shift of 45° 2) For an interface frequency between 50MHz - 99MHz, the frequency of the clock feeding the DLL should be multiplied by four to achieve an effective phase shift of 22.5°. To maximize the effective phase shift, another workaround is to use the nearest frequency above the minimum DLL input frequency to drive the DLL. You should see the following results: 1) For an interface frequency between 100MHz - 199MHz, you will get a phase-shift closer to 90° or above 45°. 2) For an interface frequency between 50MHz - 99MHz, you will get a phase-shift closer to 45° or above 22.5°. For timing analysis purposes, the DQS_PHASE_SHIFT parameters in the ALTDQ_DQS2 IP need to be set to the actual effective phase-shift value. For example, if the ALTDQ_DQS2 IP’s parameter DQS_PHASE_SETTING = 2 (90° default setting), the interface memory frequency is 178MHz, and the DLL is running at 205MHz, then 90 degree of 205MHz (1.22ns) translates to 78.14degree of 178MHz. Then, set DQS_PHASE_SHIFT = 7814 and verify the number in TimeQuest. Add the following assignment to the .qsf file: set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON This is applicable when targeting Arria® V or Cyclone® V in Quartus® II software version 13.0SP1 DP5 or newer and when targeting Stratix V or Arria V GZ in Quartus II version 13.1 or newer. The timing analysis will not be accurate without this global assignment in the .qsf file. Custom Fields values: ['novalue'] Troubleshooting 2205829611 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1 ['Arria® V FPGAs and SoCs', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']