Why do I get a pin placement error in Quartus II when assigning a user signal to a dual-purpose configuration data pin that is also used for FPPx16 configuration, even if the dual-purpose pin is reserved to be used as regular IO? - Why do I get a pin placement error in Quartus II when assigning a user signal to a dual-purpose configuration data pin that is also used for FPPx16 configuration, even if the dual-purpose pin is reserved to be used as regular IO? Description You may get such a pin placement error in the Quartus® II software if you have also enabled the Partial Reconfiguarion (PR) pins in your project. When the PR pins are enabled, the dual purpose configuration data pins used for 16-bit Fast Passive Parallel (FPPx16) mode can only be used for configuration purposes. Resolution Disable the PR pins in your project or remove the user signal location assignment to the affected dual-purpose pin. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']