Timing Violation for Arria 10 HDMI Design Over Multiple Seeds Compilation - Timing Violation for Arria 10 HDMI Design Over Multiple Seeds Compilation Description When you run the Arria 10 HDMI design over multiple Fitter seeds, the design may fail timing on this path: dcfifo:u_aud_bypass_fifo|*fifo_ram|ram_block* to this path: hdmi_tx_top:u_hdmi_tx_top|mr_hdmi_tx_core_top:u_hdmi_tx_core_top|hdmi_tx:u_hdmi_tx|hdmi_tx_altera_hdmi_151_jnt2yvq:hdmi_0|bitec_hdmi_tx:u_bitec_hdmi_tx|bitec_hdmi_tx_audio:auxiliary_encoder.audio.audio* This routing path, which is specific to the Arria 10 HDMI design, bypasses the video, audio, and auxiliary data from receiver to transmitter. Resolution To work around this issue, do one of the following steps: Turn off the Auto Global Clock option under Advanced Fitter Setting . Change the fitter effort to Standard Fit under Advanced Fitter Setting . Change the Fitter Placement Seed . This issue will be fixed in a future version of the HDMI IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 15.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']