Why does the DMA write performance of the Intel® Stratix® 10 PCIe* Avalon®-MM Hard IP implemented in Platform Designer degrade with Intel® Quartus® Prime Pro version 19.1? - Why does the DMA write performance of the Intel® Stratix® 10 PCIe* Avalon®-MM Hard IP implemented in Platform Designer degrade with Intel® Quartus® Prime Pro version 19.1? Description When using Intel® Quartus® Prime Pro version 19.1, the Intel® Stratix® 10 PCIe* Avalon®-MM Hard IP with DMA has a performance issue for DMA writes when using Platfrom Designer Avalon®-MM interconnect, which results in decreased throughput. Resolution Standalone implementations not using Platform Designer are not affected by this problem. If using Intel® Quartus® Prime Pro version 19.1, then download and install the patch 0.08 below to fix the DMA write efficiency problem. Download the Intel® Quartus® Prime Pro version 19.1 patch 0.08 for Windows (.exe) Download the Intel® Quartus® Prime Pro version 19.1 patch 0.08 for Linux (.run) Download the Readme for the Intel® Quartus® Prime Pro version 19.1 patch 0.08 (.txt) This problem is fixed starting with the Intel® Quartus® Prime Pro software version 19.2. Custom Fields values: ['novalue'] Troubleshooting 1409068226 True ['Avalon-MM Stratix® 10 Hard IP for PCI Express', 'Avalon-MM Stratix® 10 Hard IP+ for PCI Express', 'Avalon-MM Stratix® V Hard IP for PCI Express IP', 'QSYS Example Designs'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.2 19.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']