Stratix V Pci Express gen II x2 reference design - Stratix V Pci Express gen II x2 reference design Hi, i don't found this reference design (i only find x4 and x8) I tried to modify the x4 design but it gives me error s listed below. I modified in qsys: -Number of lanes x2 in the DUT instance -Application interface Avalon-ST 64-bit in the DUT instance -Lanes x2 in the APPS instance -Application interface Avalon-ST 64-bit in the APPS instance -Number of reconfiguration interfaces 3 in the PCIe Reconfig Driver Intel FPGA IP -Number of reconfiguration interfaces 3 in the Transceiver Reconfiguration Controller Intel FPGA IP -I deleted the lanes in the top level file Please help me Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 106 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL Error: HSSI PMA TX Buffer node 'top:top|altpcie_sv_hip_ast_hwtcl:dut|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst|sv_tx_pma_ch:tx_pma_insts[3].sv_tx_pma_ch_inst|tx_pma_ch.tx_pma_buf.tx_pma_buf' is not properly connected on the 'DATAOUT' port. It must be connected to one of the valid ports listed below. Info: Can be connected to I port of stratixv_io_obuf WYSIWYG Replies: Re: Stratix V Pci Express gen II x2 reference design yes it works now, thanks! Replies: Re: Stratix V Pci Express gen II x2 reference design Hi, I believe this is because the Quartus was referring to an incorrect file. If you are using an older version of design, but use it in a newer Quartus version, please try to remove the **.qip file from the project and add the newly generated ***.qsys file instead. Regards -SK