Error(17086): Verilog HDL error at alt_xcvr_native_rcfg_strm_params_qhuzj7i.sv - Error(17086): Verilog HDL error at alt_xcvr_native_rcfg_strm_params_qhuzj7i.sv Description Due to a bug in the Quartus® Prime software version 20.2 and earlier, you may see a variation of the following synthesis error if you have enabled Reconfiguration Profiles in the Arria® 10 device Native PHY IP or ATX PLL IP. This is an example Native PHY IP synthesis error Error(17086): Verilog HDL error at alt_xcvr_native_rcfg_strm_params_mcrso7a.sv(746): expression has 735 elements; expected 736 This is an example ATX PLL IP synthesis error Error(17086): Verilog HDL error at alt_xcvr_native_rcfg_strm_params_oks6upi.sv(126): expression has 115 elements; expected 116 The expression elements width will vary depending on the IP and the number of profiles enabled in your Native PHY IP and ATX PLL IP. This problem occurs when there is an odd number of Reconfiguration Profiles in your Native PHY IP or ATX PLL IP. For example 1, 3, 5, 7. Resolution To work around this problem, you can duplicate an existing Reconfiguration Profile and increase the number of profiles by one so that the total number in your Native PHY IP or ATX PLL IP is even. For example 2, 4, 6, or 8. This problem is fixed the Intel Quartus Prime Software version 20.3. Custom Fields values: ['novalue'] Troubleshooting 18011940853 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.3 20.2 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']