Why is the Stratix® 10 Serial Flash Mailbox Client IP Core not functioning properly when OSC_CLK_1 is selected as the configuration clock source? - Why is the Stratix® 10 Serial Flash Mailbox Client IP Core not functioning properly when OSC_CLK_1 is selected as the configuration clock source? Description Due to a problem in Quartus® Prime Pro software release version 18.0, the Stratix® 10 Serial Flash Mailbox Client IP Core is not able to access flash memory when OSC_CLK_1 is selected as the configuration clock source for Stratix® 10 FPGA devices. Resolution This known problem is scheduled to be fixed in future release of the Quartus® Prime Pro software. Custom Fields values: ['novalue'] Troubleshooting FB: 600990; False ['Generic Component'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.0 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']