Error: Can't fit fan-out of node <your pll output> into a single clock region - Error: Can't fit fan-out of node <your pll output> into a single clock region Description You may see this error, in the Quartus® II software, during the fitter stage if you cascade a GPLL to a MPLL in your Cyclone® IV GX design. The Quartus II software may incorrectly auto-place your cascaded MPLL in locations PLL_6 or PLL_7. These two PLL locations only support upstream PLL cascading. To ensure that your MPLL is correctly placed to support downstream cascading use a PLL location assignment to assign the required MPLL location to either PLL_5 or PLL_8. Custom Fields values: ['novalue'] Troubleshooting novalue False ['Basic Functions Clocks (Primary)'] ['novalue'] novalue novalue ['Cyclone® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']