Why does Retrain Link with Perform Equalization bit set to 1 cause the Intel® Arria® 10 FPGA PCIe 3.0 Root Port to down train to 1.0 speed? - Why does Retrain Link with Perform Equalization bit set to 1 cause the Intel® Arria® 10 FPGA PCIe 3.0 Root Port to down train to 1.0 speed? Description Retraining an Intel® Arria® 10 FPGA PCIe 3.0 Root Port link with Perform Equalization bit (Link Control 3 register 0x304 bit[0]) and Retrain Link bit (Link Control and Status register 0x90 bit[5]) set to 1 may cause the 3.0 link to down train to 1.0 speed. Unlike the Retrain Link bit, the Perform Equalization bit does not get cleared automatically after it is set to 1 , causing the LTSSM to continuously enter the Equalization state and time out. Resolution To work around this problem, clear the Perform Equalization bit to 0 during the Equalization Phase 3 (ltssmstate: 0x1E) before timeout(24ms) occurs. This problem will not be fixed in a future release of the Intel® Quartus® Prime Software. Custom Fields values: ['novalue'] Troubleshooting FB: 546097; True ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 17.1.1 ['Arria® 10 FPGAs and SoCs', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']