Is the jitter of the low-voltage differential signaling (LVDS) phase-locked loop (PLL) output different from the regular PLL output? (APEXTM 20KE, LVDS, PLL) - Is the jitter of the low-voltage differential signaling (LVDS) phase-locked loop (PLL) output different from the regular PLL output? (APEXTM 20KE, LVDS, PLL) Description Yes. The LVDS PLLs are high-performance PLLs designed for low jitter. These PLLs have lower jitter (typically 20 ps) in their output clock as compared to regular (non-LVDS) PLLs. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']