Why does the F-Tile JESD204C Agilex® 7 FPGA IP Design Example simulation fail with signal rx_gb_underflow_err being asserted? - Why does the F-Tile JESD204C Agilex® 7 FPGA IP Design Example simulation fail with signal rx_gb_underflow_err being asserted? Description Due to a problem in the ModelSim*-Altera® FPGA Edition 2021.4 and Questa* Altera® FPGA Edition 2022.1, a variation in rx_phy_clk frequency leads to the signal rx_gb_underflow_err being asserted. This problem is observed only in the following variant: L = 16, M = 8, F = 2, DATA RATE/L = 32000.000000Mbps, FCLK_MULP = 1, WIDTH_MULP = 4 Resolution This problem impacts Intel® Quartus® Prime Software IP versions 22.2 and 22.3. To work around this problem: For ModelSim*, run the simulation using v2022.1 instead of v2021.4. For Questa*, run the simulation using v2021.3 instead of v2022.1. This problem has been fixed in the ModelSim* Intel® FPGA Edition and Questa* Intel® FPGA Edition 22.4. Custom Fields values: ['novalue'] Troubleshooting 15011431167 False ['JESD204B IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.4 22.2 ['Agilex™ 7 FPGAs and SoCs'] ['Simulation Dev Tools ModelSim', 'Simulation Dev Tools Questa'] ['novalue'] ['novalue']