What is the recommended termination guideline for mem_reset_n when using DDR3 SDRAM controller with UniPHY? - What is the recommended termination guideline for mem_reset_n when using DDR3 SDRAM controller with UniPHY? Description Altera® does not recommend terminating the mem_reset_n signal. DDR3 DIMMs typically do not use any termination on the memory reset signal. Refer to the memory vendor datasheet for any memory reset termination guidelines. Resolution Related Articles Can I use a USB Blaster download cable for AES key programming? Timing violation when enable 'Extra Timing Report Clock' in DDR3 UniPHY based controller Can I place bonded transceiver channels non-contiguously in Stratix® V and Arria® GZ transceiver devices? Custom Fields values: ['novalue'] Troubleshooting N/A False ['Memory Interfaces with UniPHY'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Arria® V FPGAs and SoCs', 'Stratix® III FPGAs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']