Why does Agilex™ 7 SoC FPGA fail to access DDR space when HPS EMIF is enabled with Half Rate Converter (HRC) On and Quarter Rate? - Why does Agilex™ 7 SoC FPGA fail to access DDR space when HPS EMIF is enabled with Half Rate Converter (HRC) On and Quarter Rate? Description Due to a problem with u-boot-spl(u-boot-socfpga-v2022.01) for Agilex™ 7 SoC FPGA, you may not be able to access all HPS DDR space when HPS EMIF is enabled with Half Rate Converter (HRC) On and Quarter Rate. For example, if HPS EMIF is a 2GB configuration, HPS can only access the first half of 2GB, and the second half of 2GB is just an alias for the first half. Resolution To work around this problem, you need to change the source code in u-boot-socfpga/drivers/ddr/altera/sdram_agilex.c(81) from update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4); To update_value |= 0x4; Additional Information This problem has been fixed in with u-boot-spl(u-boot-socfpga-v2023.01). Custom Fields values: ['novalue'] Troubleshooting 15011830300 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.2 22.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']