Compilation error while assigning pins for the clocks - Compilation error while assigning pins for the clocks Hi, I have generated the design example for Low latency ethernet 10g mac intel fpga ip-- 10GBASE-R Example design(Arria10) by following the below document. https://www.intel.com/content/www/us/en/docs/programmable/683063/19-1-19-1/10gbase-r-ethernet-design-example-for.html While doing the compilation, I am getting the below error. Error(175001): The Fitter cannot place 1 HSSI_PMA_CDR_REFCLK_SELECT_MUX, which is within Transceiver Native PHY Intel Arria 10/Cyclone 10 FPGA IP altera_eth_10gbaser_phy_altera_xcvr_native_a10_191_fr4v7ey. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(175006): There is no routing connectivity between the HSSI_PMA_CDR_REFCLK_SELECT_MUX and destination HSSI_PMA_CDR_PLL Error(175022): The HSSI_PMA_CDR_REFCLK_SELECT_MUX could not be placed in any location to satisfy its connectivity requirements Error(175006): There is no routing connectivity between source HSSI_REFCLK_CLUSTER and the HSSI_PMA_CDR_REFCLK_SELECT_MUX Error(175022): The HSSI_PMA_CDR_REFCLK_SELECT_MUX could not be placed in any location to satisfy its connectivity requirements Error(175001): The Fitter cannot place 1 HSSI_PMA_CDR_REFCLK_SELECT_MUX, which is within Transceiver Native PHY Intel Arria 10/Cyclone 10 FPGA IP altera_eth_10gbaser_phy_altera_xcvr_native_a10_191_fr4v7ey. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(175006): There is no routing connectivity between the HSSI_PMA_CDR_REFCLK_SELECT_MUX and destination HSSI_PMA_CDR_PLL Error(175022): The HSSI_PMA_CDR_REFCLK_SELECT_MUX could not be placed in any location to satisfy its connectivity requirements Error(175006): There is no routing connectivity between source HSSI_REFCLK_CLUSTER and the HSSI_PMA_CDR_REFCLK_SELECT_MUX Error(175022): The HSSI_PMA_CDR_REFCLK_SELECT_MUX could not be placed in any location to satisfy its connectivity requirements “. Details: Quartus used : Quartus prime 22.2 Board :Intel arria 10 GX development board Device : 10AX115S2F45I1SG. Below are the pin assignments Name Pin assigned csr_clk 125Mhz BD24 clk_125 ref_clk_clk 322.265625Mhz AA37 REFCLK_SFP(modified using clock controller) Replies: Re: Compilation error while assigning pins for the clocks Hi, I’m glad that your issue has been resolved, I now transition this thread to community support. If you have a new question. Please login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thank you, Kshitij Goel Replies: Re: Compilation error while assigning pins for the clocks Hi, I have assigned Pin AN8 (REFCLK_FMCA_P) modified using clock controller to the ref_clk_clk and the compilation was successful. Thank you. Replies: Re: Compilation error while assigning pins for the clocks Hi, Can you please try with the latest Quartus version 23.3? Thank you, Kshitij Goel