RapidIO IP Core Device and Assembly Register Values Might Lose MSBs - RapidIO IP Core Device and Assembly Register Values Might Lose MSBs Description In RapidIO variations that are generated with Qsys and target a device other than a Cyclone IV GX device, the device and assembly register (capability registers at offsets 0x00 to 0x0C) non-zero field values whose decimal (base 10) representation has four or fewer decimal digits are truncated such that the two most significant decimal digits are zeroed. Leftmost zero digits are ignored for purposes of this count. No warning message is generated. In the case of the device revision ID field, the two leftmost decimal digits are truncated if the decimal representation has eight or fewer decimal digits, rather than four or fewer decimal digits. For example, if the device revision ID is 0x5F54433, the decimal representation is 99,959,859. This representation has eight digits, so the two most significant digits are truncated, resulting in the decimal value 959859. In an affected configuration, if a device or assembly register value has four or fewer significant decimal digits (leftmost zeroes are not counted), the actual configured register value is missing the two most significant decimal digits. In the case of the device revision ID, if the value has eight or fewer significant decimal digits, the actual configured register value is missing the two most significant decimal digits. In these cases, the device and assembly register values are incorrect. Resolution To correct this issue in your RapidIO MegaCore function, after you generate your Qsys system and before you compile, follow these steps: Open the file < sysdir > /synthesis/submodules/altera_rapidio_ < variation_string > .v in a text editor. < sysdir > is the output directory path you specify in Qsys, and < variation_string > is an arbitrary alphanumeric string generated by Qsys to specify your RapidIO variation. Correct the values of the signals that correspond to the individual register fields according to the register-field signal-name correspondence shown in the following table. Specify the correct hexadecimal value for each parameter. Signals that Correspond to Device and Assembly Register Fields Register Field Signal Name Format of Corrected Value Device ID signal_wire10 16’hXXXX Vendor ID signal_wire11 16’hXXXX Revision ID signal_wire12 32’hXXXXXXXX Assembly ID signal_wire13 16’hXXXX Assembly Vendor ID signal_wire14 16’hXXXX Assembly Revision ID signal_wire15 16’hXXXX Extended feature pointer signal_wire16 16’hXXXX This issue is fixed in version 11.0 of the RapidIO MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 11.0 10.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']