Default tCCD for LPDDR2 Devices Hard Codes to 2 Cycles - Default tCCD for LPDDR2 Devices Hard Codes to 2 Cycles Description This problem affects LPDDR2 products. This issue applies to LPDDR2 interfaces, when an LPDDR2-S2 memory device is used. Generated example designs always set tCCD=2 cycles for LPDDR2 devices, but the minimum tCCD supported for LPDDR2-S2 is 1 cycle. Having tCCD=1 for LPDDR2-S2 devices may impact design performance. Resolution The workarounds for this issue are described below. For designs using the High Performance Controller II (HPCII): In a text editor, open the file /dut_example_design/example_project/dut_example/submodules/ *_example_if0_c0.v . Search for .CFG_TCCD (2) and change it to .CFG_TCCD (1) . For designs using the hard memory controller: In a text editor, open the file /dut_example_design/example_project/dut_example/submodules/ *_example_if0.v . Search for .ENUM_MEM_IF_TCCD (“TCCD_2”) and change it to .ENUM_MEM_IF_TCCD (“TCCD_1”) . This issue will be fixed in a future version. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']