Why does simulation elaboration fail with port width mismatch for the F-tile Ethernet Hard IP 400GE-8 DR example design generated with VHDL when using QuestaSim* or Riviera-PRO* simulator? - Why does simulation elaboration fail with port width mismatch for the F-tile Ethernet Hard IP 400GE-8 DR example design generated with VHDL when using QuestaSim* or Riviera-PRO* simulator? Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1, when running simulation for the F-Tile Ethernet Hard IP 400GE-8 Dynamic Reconfiguration (DR) Example Design generated with VHDL and using Questa* Sim or Riviera-PRO* simulator, you may observe the following port width mismatch error during elaboration: # Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/eth_f_hw/IP_INST[0]/hw_ip_top/dut File: ./eth_f_hw_ip_top_400g.sv Line: 707 # ** Fatal: (vsim-3363) The array length (4) of VHDL port 'anlt_link' does not match the width (8) of its Verilog connection (1st connection). # Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/eth_f_hw/IP_INST[0]/hw_ip_top/dut File: ./eth_f_hw_ip_top_400g.sv Line: 707 # FATAL ERROR while loading design # Error loading design Error loading design This occurs due to a mismatch between the array length of the VHDL port and the width of its Verilog connection in the generated design. Resolution To work around this problem, you may use one of the following methods: Update the MAX_ETHPORT parameter in the eth_f_hw_ip_top module to 4: parameter MAX_ETHPORT = 4; (Change the value to 4 as shown above.) Use the following suppress switch in the vsim do file: elab -suppress 3363 This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 14027458704 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 26.1 ['Agilex™ 7 FPGAs and SoCs'] ['Simulation Dev Tools Questa'] ['novalue'] ['novalue']