Qsys Pro-Generated SVD File of an HPS Component Does Not Include Register Map Information for the Slave Interfaces - Qsys Pro-Generated SVD File of an HPS Component Does Not Include Register Map Information for the Slave Interfaces Description For an HPS component, the Quartus ® Prime Pro Edition software\'s Qsys Pro beta feature generates an SVD file that only contains register map information for the master interface. The SVD file does not contain register map information for the slave interfaces that are connected to the HPS component. Resolution None. This issue will be resolved in a future release of the Quartus Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting FB365186; True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.0 16.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']