Why do I see an early assertion of reset_status_n signal on R-tile Avalon® Streaming FPGA IP for PCI Express* on PIPE direct mode? - Why do I see an early assertion of reset_status_n signal on R-tile Avalon® Streaming FPGA IP for PCI Express* on PIPE direct mode? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4 and earlier, you may see abnormal reset_status_n early assertion in R-Tile Avalon® Streaming FPGA IP in PIPE direct mode. Resolution This problem is planned to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15017061593 False ['R-Tile Avalon-ST for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.1 23.4 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']