Are the Partial Reconfiguration output pins on Stratix V, Arria V and Cyclone V devices configured as Open Drain by default, when these pins are enabled in my Quartus II project? - Are the Partial Reconfiguration output pins on Stratix V, Arria V and Cyclone V devices configured as Open Drain by default, when these pins are enabled in my Quartus II project? Description In Quartus® II software versions 12.1 and earlier, if the Partial Reconfiguration (PR) pins are enabled for Stratix® V, Arria® V or Cyclone® V devices, the outputs will not be configured as Open Drain, and they will be powered by the VCCIO supply of the bank that they reside in. Resolution Open Drain functionality will be provided as an option for these pins in a future version of the Quartus II software. Related Articles When using Partial Reconfiguration are the PR_DONE, PR_READY, PR_ERROR, and PR_REQUEST pins powered by VCCPGM or VCCIO? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']