Why does my downstream IOPLL fail to lock when cascading IOPLLs in Intel® Stratix® 10 devices? - Why does my downstream IOPLL fail to lock when cascading IOPLLs in Intel® Stratix® 10 devices? Description When cascading IOPLLs in Intel® Stratix® 10 devices, if the downstream IOPLL has calibrated before the upstream IOPLL or if the upstream IOPLLs calibration has failed, this may cause cause the downstream IOPLL not to lock. Resolution Connect the permit_cal input of the downstream IOPLL to the locked output of the upstream IOPLL when cascading IOPLLs to prevent the downtream IOPLL calibrating before the upstream IOPLL has completed calibration and has locked to its incoming clock. Custom Fields values: ['novalue'] Troubleshooting FB: 528586; False ['IOPLL IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.0 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']