Which index of the fclk[1..0] and loaden[1..] signals should I use when implementing a multi-bank, wide TX interface using the Stratix 10 Altera LVDS SERDES IP in external pll mode? - Which index of the fclk[1..0] and loaden[1..] signals should I use when implementing a multi-bank, wide TX interface using the Stratix 10 Altera LVDS SERDES IP in external pll mode?
Description For multi-bank wide TX configurations with external pll using Stratix® 10 device LVDS IP, only the second pair of clocks from the external pll (pair indexed by [1]) are valid Resolution This will be updated in the next version of the Intel® Stratix 10 device High-Speed LVDS I/O User Guide
Custom Fields values:
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Troubleshooting
FB: 456476;
False
['novalue']
['FPGA Dev Tools Quartus® Prime Software Pro']
17.1
17.0
['Stratix® 10 FPGAs and SoCs']
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['novalue']
['novalue'] - 2021-08-25
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