Why might the Low Latency 40G and 100Gbps Ethernet MAC pause quanta time be shorter than expected? - Why might the Low Latency 40G and 100Gbps Ethernet MAC pause quanta time be shorter than expected? Description The IEEE standard 802.3 figure 31b-2 states that the pause timer should not be loaded with a received quanta value until the transmitter is idle. This spec aspect was not implemented in the Low Latency 40G and 100Gbps Ethernet MAC and PHY Megacore® Function flow control implementation. Therefore, if the TX is not idle when the pause quanta are loaded, the requested pause time may be shorter than expected. Resolution This problem is not currently scheduled to be fixed. Custom Fields values: ['novalue'] Troubleshooting FB: 396193; True ['Ethernet', 'Low Latency 40G 100G Ethernet'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 15.1 ['Arria® 10 FPGAs and SoCs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']