Why does the MIPI CSI-2 IP Design Example fail to migrate from the Quartus® Prime Pro Edition Software version 24.1 to 24.3? - Why does the MIPI CSI-2 IP Design Example fail to migrate from the Quartus® Prime Pro Edition Software version 24.1 to 24.3? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 when performing an IP upgrade from version 24.1, the MIPI CSI-2 IP Design Example will fail. The following error message will appear: csi_rx.ls_clk must be connected to a clock output csi_rx.ls_rst must be connected to a reset output Resolution To work around this problem, please regenerate the MIPI CSI-2 IP Design Example via the IP catalog in the Quartus® Prime Pro Edition software version 24.3. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16026431694 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 24.3 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']