Why doesn't the Intel Arria 10 DDR4 x4 Configuration didn't follow dq/dqs pairing as pinout placement - Why doesn't the Intel Arria 10 DDR4 x4 Configuration didn't follow dq/dqs pairing as pinout placement
Description Users might configurate EMIF x4 DQ group and Quartus Prime automatically assigns the PIN and fitter successfully. But Dq pin assigment didnt follow the PIN assignment rules from the PIN_OUT file. Resolution In Arria 10 IO architecture for X4 DQ pins users allow to assign any pin location within a lane.
Custom Fields values:
['novalue']
Troubleshooting
FB: 445265;
False
['novalue']
['novalue']
novalue
novalue
['Arria® 10 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2021-08-25
external_document