Why does the Hard IP Reconfiguration Interface deadlock when using the P-Tile Intel® FPGA IP for PCI Express*? - Why does the Hard IP Reconfiguration Interface deadlock when using the P-Tile Intel® FPGA IP for PCI Express*? Description Due to a limitation in the P-Tile Intel® FPGA IP for PCI Express* with the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier version, the Hard IP Reconfiguration Interface can deadlock with " hip_reconfig_waitrequest_o " asserted. The problem cannot be resolved by resetting the P-Tile Intel® FPGA IP for PCI Express* using the " pin_perst_n ". Resolution To avoid this problem, ensure that the Hard IP Reconfiguration Interface is not used during the assertion of " pin_perst_n ". This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.3. Custom Fields values: ['novalue'] Troubleshooting 00696522 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 22.2 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 DX FPGA'] ['novalue'] ['novalue'] ['novalue']