LPDDR2 Interfaces on Arria V SoC Devices May Fail Postamble Timing - LPDDR2 Interfaces on Arria V SoC Devices May Fail Postamble Timing
Description This problem affects LPDDR2 products. Due to preliminary timing models, LPDDR2 interfaces on Arria V SoC devices may fail Postamble Timing in Report DDR . Resolution The workaround for this issue is to ignore the postamble timing failures. This issue will be fixed in a future version.
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Troubleshooting
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True
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['FPGA Dev Tools Quartus II Software']
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13.0.1
['Arria® V FPGAs and SoCs']
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['novalue']
['novalue'] - 2021-08-25
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