Implementing the Triple-Speed Ethernet FPGA IP - 12 Minutes This online course will instruct you on how to build 10/100/1000 Mb Ethernet solutions targeting Altera® FPGAs using the Quartus® Prime software. To do this, you will learn how to customize the Altera® Triple Speed Ethernet (TSE) FPGA IP for your Ethernet application using the Quartus software TSE FPGA IP parameter editor. After customization, you need to connect your IP into your FPGA design. To assist with this, this course will show you how to generate design examples from within the same parameter editor window. These design examples are fully function designs that can run in simulation and hardware. Along with demonstrating the IP connections, they also help you understand and verify IP functionality. Course Objectives At course completion, you will be able to: Configure a stand-alone TSE FPGA IP implementation and incorporate it into a design Generate design examples to execute in simulation or in hardware Skills Required Understanding of the Ethernet technology specifications Familiarity with FPGA/CPLD design flow Familiarity with the Quartus Prime software Some familiarity with Platform Designer If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com Reference Course Code: FPGA_OTSE1116P2. FPGA_OTSE1116P2. <p>Implementing the Triple-Speed Ethernet FPGA IP</p>