Why do I see additional GPIO blockage in bank 3A of Agilex® 7 FPGA M-Series? - Why do I see additional GPIO blockage in bank 3A of Agilex® 7 FPGA M-Series? Description You will see additional I/O bank blockage at BL4, BL5, BL6, and part of BL7 in bank 3A when you route the NoC PLL lock signal of NoC Clock Control IP to core fabric. You will not see additional I/O bank blockage in the bottom I/O bank. Resolution To work around this problem, follow one of the methods below. Do not route the NoC PLL lock signal of NoC Clock Control IP to core fabric in your full project. Use this signal only in debug projects. Place GPIO in pin index [89:95] in BL7 of bank 3A. Custom Fields values: ['novalue'] Troubleshooting 14027258787 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3.1 ['Agilex™ 7 FPGA M-Series'] ['novalue'] ['novalue'] ['novalue']