Why does the XCVR_REFCLK_PIN_TERMINATION, DC_COUPLING_INTERNAL_100_OHM assignment fail in the Quartus® II software version 12.0? - Why does the XCVR_REFCLK_PIN_TERMINATION, DC_COUPLING_INTERNAL_100_OHM assignment fail in the Quartus® II software version 12.0? Description The XCVR_REFCLK_PIN_TERMINATION, DC_COUPLING_INTERNAL_100_OHM assignment fails in the Quartus® Ii software version 12.0 due to an error in the Transceiver PHY Intel® FPGA IP User Guide. " Table 6-4. Transceiver and PLL Assignments for Stratix® V Devices" of the transceiver PHY IP userguide details the constraint as"DC_COUPLING_INTERNAL_100_OHM". The correct constraint is "DC_COUPLING_INTERNAL_100_OHMS" Resolution This error has been fixed in the Quartus® II software v12.0. Custom Fields values: ['novalue'] Troubleshooting FB : 60744 False ['Generic Component'] ['FPGA Dev Tools Quartus® Prime Software'] 12.0 12.0 ['Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']