Why are the Ax, Ay, Az, and Chainin ports missing from the block symbol and HDL instantiation template of the Intel® Stratix® 10 Native Floating Point DSP IP? - Why are the Ax, Ay, Az, and Chainin ports missing from the block symbol and HDL instantiation template of the Intel® Stratix® 10 Native Floating Point DSP IP? Description Due to a problem with the Intel® Stratix® 10 Native Floating Point DSP IP in Intel® Quartus® Prime Pro software version 17.1, you may observe that the Ax, Ay, Az, and Chainin ports are missing from the block symbol and HDL instantiation template if the IP is configured with Vector Mode 2. Resolution This problem has been fixed starting in v18.0 of the Intel Quartus Prime Pro software. Custom Fields values: ['novalue'] Troubleshooting FB: 541680; False ['Native Floating Point DSP Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.0 17.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']