Qsys interconnect wait for WLAST might deadlock some AXI masters - Qsys interconnect wait for WLAST might deadlock some AXI masters
Description The master-side of the Qsys interconnect waits for a WLAST signal before it asserts an AWREADY signal to minimize area. This might cause deadlock for some AXI masters. Resolution Insert a pipelined AXI bridge between the master and the interconnect
Custom Fields values:
['novalue']
Troubleshooting
FB405666;
True
['novalue']
['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard']
18.1
16.1
['Programmable Logic Devices']
['novalue']
['novalue']
['novalue'] - 2021-08-25
external_document