How do I determine a loss of alignment when using the Intel® Stratix® 10 E-Tile Hard IP for Ethernet Intel® FPGA IP in 100G mode with PCS (528,514)RSFEC or PCS (544,514)RSFEC IP? - How do I determine a loss of alignment when using the Intel® Stratix® 10 E-Tile Hard IP for Ethernet Intel® FPGA IP in 100G mode with PCS (528,514)RSFEC or PCS (544,514)RSFEC IP? Description Currently there is no exposed port on the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel® FPGA IP when in 100G mode with either PCS (528,514)RSFEC or PCS (544,514)RSFEC IP that indicates a loss of alignment. Resolution This has been fixed in the Intel® Quartus® Prime Software v18.1.1. Custom Fields values: ['novalue'] Troubleshooting FB: 598421; True ['Ethernet'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1.1 18.1 ['Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']